1. Field of the Invention
The present invention relates to a method of fabricating a sample wafer and, particularly, to a method of fabricating a sample wafer for forming sample transistors having different characteristics.
2. Description of Related Art
Heretofore, when determining the impurity concentration of an N-channel transistor and a P-channel transistor to be formed on a wafer, each transistor level is made differently by controlling an impurity channel doping amount (well impurity ion doping amount) for threshold control on each wafer.
FIG. 7 is a flowchart showing a method of fabricating a sample wafer according to a related art. According to the method, the process first coats a resist on a wafer (S101) and performs exposure and development in a predetermined region (S102). Then, the process implants a P-type ion, for example, into a formed resist pattern (S103) and removes the resist (S104). After that, the process coats another resist (S105), performs exposure and development (S106), then implants an N-type ion (S107), and finally removes the resist (S108).
In the above method, the transistors with different levels are formed on different wafers. Specifically, a wafer having the characteristics (Tr1) that the ON-current of an N-channel transistor is small and the ON-current of a P-channel transistor is large, a wafer having the characteristics (Tr2) that the ON-current of an N-channel transistor is large and the ON-current of a P-channel transistor is large, a wafer having the characteristics (Tr3) that the ON-current of an N-channel transistor is large and the ON-current of a P-channel transistor is small, and a wafer having the characteristics (Tr4) that the ON-current of an N-channel transistor is small and the ON-current of a P-channel transistor is small are formed as shown in FIG. 1, and if a desired level of leakage current, switching characteristics or the like is obtained, a channel doping amount which has the intermediate value (Tr5) of them is estimated (cf. Carver Mead (author), Shiro Usui and Hiroo Yonezu (translators), “Analog VLSI and Neural Systems”, TOPPAN PRINTING Co., Ltd. Appendix CMOS fabrication method).
In this method, it is necessary to form a wafer which includes a transistor in which a P-type impurity ion is doped at a high concentration and a transistor in which an N-type impurity ion is doped at a low concentration, a wafer which includes a transistor in which a P-type impurity ion is doped at a high concentration and a transistor in which an N-type impurity ion is doped at a high concentration, a wafer which includes a transistor in which a P-type impurity ion is doped at a low concentration and a transistor in which an N-type impurity ion is doped at a low concentration, and a wafer which includes a transistor in which a P-type impurity ion is doped at a low concentration and a transistor in which an N-type impurity ion is doped at a high concentration.
Because the above-described method of forming a level pattern prepares a wafer for each level, it is difficult to suppress variations between substrates. Further, because it requires the same number of wafers as levels, which is four in the above-described example, the number of diffusion steps is large to cause higher costs and the length of tester usage time is long for evaluating different sample wafers, thus taking a long time for testing.